Cost of testing a chip varies between different products, but it is often a major portion of the production cost nonetheless. Most chips still rely heavily on ATE for the testing, the cost of which depends on the amount of test time needed for a particular chip; more complex designs and more thorough tests invariably drives the test cost up. ATE driven tests are also significantly constrained by performance of the ATE and natural limitations of the test rigging, most chips can only be tested at slow test speed which is significantly lower than the actual designed operating speed.
Accelerated Memory Built-In Self-Test (AMBIST) is an embedded on-chip IP with two main purposes:
AMBIST test patterns are generated with an SHS hash function; each the test pattern generated is highly unique, and it is with extremely low probability any the test pattern ever repeats; the test patterns also demonstrate very high quality pseudorandom characteristics, all thanks to the quality of the SHS algorithms; in addition, each the test pattern generated may also be inverted if necessary. With these unique qualities, AMBIST test patterns are specially suited for testing large memory devices that are very common today; it offers almost never repeating test patterns with very good pseudorandom characteristics; and every memory bit can be covered with logic-0, logic-1, 1->0 transition, and 0->1 transition tests.
The capabilities of AMBIST can be just as readily adopted as a Logic BIST. One easiest way is to couple with the tried and tested scan test methodology by replacing the traditionally external software ATPG with AMBIST generated test patterns on-chip; in other words, using the AMBIST as an on-chip ATPG for loading the scan-chains, therefore, eliminating the test-time consuming task of scanning-in external test patterns with ATE.
AMBIST further uses the SHS function to hash all captured response data or all written memory content to make a unique test-result signature - typically only 256 bits - for verification of the test result. The high quality of the SHS algorithms ensures with extreme high probability that any erroneous test results in a test set would result in an incorrect test-result signature be generated; thus, whether or not a chip pass a particular test set can be verified just with the computed test-result signature. External test system only needs to read out the test-result signature from an AMBIST embedded chip to know whether the chip passed a particular test set; the traditional task of reading out test responses from a chip and verify with ATE - which consumes a great amount of test-time and test resources - is no longer necessary with AMBIST based chips.
An AMBIST based chip is capable of being almost completely autonomous in the testing. It does not need any test vector inputs from an external test system, nor does it have to send all the test response data back to the external test system for verification; simple initiation and the verification of the short test-result signature is all the test-time required of the external test system. Most the expensive and sophisticated capabilities of traditional ATE just do not seem to be needed with an AMBIST embedded chip. Much simpler and cheaper testers and systems should be adopted for testing AMBIST based chips; and the systems could be so dramatically different from ATE as we know today, it could be a source of controversy to call them the same; so perhaps, testers for AMBIST based chips are better called TVD (Test Verification Device) instead - since that verifying the test result by reading a short test-result signature from a chip is all that they need to do. Test cost with AMBIST based chips may also have to be redefined; since the test-time as we know today will no longer be a practical matter, the test cost may even become a minor factor amongst all the costs of production.
AMBIST typically generates 512 bits of test pattern at a time, and typically takes less than 100 clock cycles for the task; hashing of each 512-bit test response data block also takes less than 100 clock cycles. A demo implementation of AMBIST on a FPGA, running the entire system on a single 20 MHz clock and testing a 1 MB block of memory - with AMBIST generated test patterns and covering every memory bits with logic-1 and logic-0 - took about 0.3 seconds test-time on-chip. Today's ASIC processes can easily run the test clock at 100 MHz or more; translated to the on-chip test-time, even a 1 GB memory block only needs about a minute to test with AMBIST; and with more advanced clocking scheme, even higher performance could be achievable. More importantly, AMBIST allows today's advanced chips to perform tests at speed; one thing very difficult and expensive to achieve with ATE.
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